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NCV7356 Advance Information Single Wire CAN Transceiver
The NCV7356 is a physical layer device for a single wire data link capable of operating with various Carrier Sense Multiple Access with Collision Resolution (CSMA/CR) protocols such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor and/or dedicated logic devices which use the network. The network shall be able to operate in either the normal data rate mode or a high-speed data download mode for assembly line and service data transfer operations. The high-speed mode is only intended to be operational when the bus is attached to an off-board service node. This node shall provide temporary bus electrical loads which facilitate higher speed operation. Such temporary loads should be removed when not performing download operations. The bit rate for normal communications is typically 33 kbit/s, for high-speed transmissions like described above a typical bit rate of 83 kbit/s is recommended. The NCV7356 is designed in accordance to the Single Wire CAN Physical Layer Specification GMW3089 V2.3 and supports many additional features like undervoltage lockout, timeout for faulty blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current.
Features http://onsemi.com MARKING DIAGRAM
14 14 1 SO-14 D SUFFIX CASE 751A 1 A WL Y WW = Assembly Location = Wafer Lot = Year = Work Week NCV7356 AWLYWW
PIN CONNECTIONS
GND 1 TxD 2 MODE0 3 MODE1 4 RxD 5 14 GND 13 NC 12 CANH 11 LOAD 10 VBAT 9 8 (Top View) INH GND
* * * * * * * * * * * * * * * * * * *
Fully Compatible with J2411 Single Wire CAN Specification 60 mA (max) Sleep Mode Current Operating Voltage Range 5.0 to 27 V Up to 100 kbps High-Speed Transmission Mode Up to 40 kbps Bus Speed Selective BUS Wake-Up Logic Inputs Compatible with 3.3 V and 5 V Supply Systems Control Pin for External Voltage Regulators Standby to Sleep Mode Timeout Low RFI Due to Output Wave Shaping Fully Integrated Receiver Filter Bus Terminals Proof Against Short-Circuits and Transients Loss of Ground Protection Protection Against Load Dump, Jump Start Thermal Overload and Short Circuit Protection ESD Protection of 4.0 kV on CAN Pin (2.0 kV on Any Other Pin) Undervoltage Lock Out Bus Dominant Timeout Feature NCV Prefix for Automotive and Other Applications Requiring Site and Change Control
NC 6 GND 7
ORDERING INFORMATION
Device NCV7356D NCV7356DR2 Package SOIC-14 SOIC-14 Shipping 55 Units / Rail 1000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Semiconductor Components Industries, LLC, 2004
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September, 2004 - Rev. P2
Publication Order Number: NCV7356/D
NCV7356
VBAT
INH
NCV7356
5 V Supply and References Biasing and VBAT Monitor
Reverse Current Protection
RC-Osc
Wave Shaping CAN Driver TxD Time Out CANH
Feedback Loop
Input Filter
MODE0
LOAD MODE CONTROL Receive Comparator Loss of Ground Detection
MODE1
RxD RxD Blanking Time Filter
Reverse Current Protection
GND
Figure 1. Block Diagram
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NCV7356
PACKAGE PIN DESCRIPTION
Pin 1, 7, 8, 14 2 3 4 5 6, 13 9 10 11 12 Symbol GND TXD MODE0 MODE1 RXD NC INH VBAT LOAD CANH Ground Transmit data from microprocessor to CAN. Operating mode select input 0. Operating mode select input 1. Receive data from CAN to microprocessor. No Connection Control pin for external voltage regulator (high voltage high side switch) Battery input voltage. Resistor load (loss of ground detection low side switch). Single wire CAN bus pin. Description
Functional Description
TxD Input Pin
Sleep Mode
TxD Polarity
* TxD = logic 1 (or floating) on this pin produces an
undriven or recessive bus state (low bus voltage) * TxD = logic 0 on this pin produces either a bus normal or a bus high voltage dominant state depending on the transceiver mode state (high bus voltage) If the TxD pin is driven to a logic low state while the sleep mode (Mode 0 = 0 and Mode 1 = 0) is activated, the transceiver can not drive the CANH pin to the dominant state. The transceiver provides an internal pull up current on the TxD pin which will cause the transmitter to default to the bus recessive state when TxD is not driven. TxD input signals are standard CMOS logic levels.
Timeout Feature
Transceiver is in low power state, waiting for wake-up via high voltage signal or by mode pins change to any state other than 0,0. In this state, the CANH pin is not in the dominant state regardless of the state of the TxD pin.
High-Speed Mode
This mode allows high-speed download with bitrates up to 100 Kbit/s. The output waveshaping circuit is disabled in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in high-speed mode are able to drive reduced bus resistance in this mode.
High Voltage Wake-Up Mode
In case of a faulty blocked dominant TxD input signal, the CANH output is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission is continued by next TxD L to H transition without delay.
MODE0 and MODE1 Pins
This bus includes a selective node awake capability, which allows normal communication to take place among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by controlling the signal voltages such that all nodes must wake-up when they receive a higher voltage message signal waveform. The communication system communicates to the nodes information as to which nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low power "sleep" state. Communication at the lower, normal voltage levels shall not disturb the sleeping nodes.
Normal Mode
The transceiver provides a weak internal pull down current on each of these pins which causes the transceiver to default to sleep mode when they are not driven. The mode input signals are standard CMOS logic level for 3.3V and 5V supply voltages.
MODE0 L H L H MODE1 L L H H Sleep Mode High-Speed Mode High Voltage Wake-Up Normal Mode Mode
Transmission bit rate in normal communication is 33 Kbits/s. In normal transmission mode the NCV7356 supports controlled waveform rise and overshoot times. Waveform trailing edge control is required to assure that high frequency components are minimized at the beginning of the downward voltage slope. The remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time constant of the total bus load.
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NCV7356
RxD Output Pin CAN BUS Input/Output Pin
Logic data as sensed on the single wire CAN bus.
RxD Polarity
* RxD = logic 1 on this pin indicates a bus recessive *
state (low bus voltage) RxD = logic 0 on this pin indicates a bus normal or high voltage bus dominant state
Wave Shaping in Normal and High Voltage Wake-Up Mode
RxD in Sleep Mode
RxD does not pass signals to the microprocessor while in sleep mode until a valid wake-up bus voltage level is received or the MODE0 and MODE 1 pins are not 0, 0 respectively. When the valid wake-up bus voltage signal awakens the transceiver, the RxD pin signals an interrupt (logic 0). If there is no mode change within 250 ms (typ), the transceiver re-enters the sleep mode. When not in sleep mode all valid bus signals will be sent out on the RxD pin. RxD will be placed in the undriven or off state when in sleep mode.
RxD Typical Load
Wave shaping is incorporated into the transmitter to minimize EMI radiated emissions. An important contributor to emissions is the rise and fall times during output transitions at the "corners" of the voltage waveform. The resultant waveform is one half of a sin wave of frequency 50-65 kHz at the rising waveform edge and one quarter of this sin wave at falling or trailing edge.
Wave Shaping in High-Speed Mode
Wave shaping control of the rising and falling waveform edges are disabled during high-speed mode. EMI emissions requirements are waived during this mode. The waveform rise time in this mode is less than 1.0 ms.
Short Circuits
Resistance: 2.7 kW Capacitance: < 25 pF
Bus LOAD Pin Resistor ground connection with internal open-on-loss- of-ground protection
If the CAN BUS pin is shorted to ground for any duration of time, the current is limited as specified in the Electrical Characteristics Table until an overtemperature shutdown circuit disables the output high side drive source transistor preventing damage to the IC.
Loss of Ground
When the ECU experiences a loss of ground condition, this pin is switched to a high impedance state. The ground connection through this pin is not interrupted in any transceiver operating mode including the sleep mode. The ground connection only is interrupted when there is a valid loss of ground condition. This pin provides the bus load resistor with a path to ground which contributes less than 0.1 V to the bus offset voltage when sinking the maximum current through one load resistor. The transceiver's maximum bus leakage current contribution to Vol from the LOAD pin when in a loss of ground state is 50 mA over all operating temperatures and 3.5 < VBAT < 27 V.
VBAT Input Pin (Vehicle Battery Voltage)
In case of a valid loss of ground condition, the LOAD pin is switched into high impedance state. The CANH transmission is continued until the undervoltage lock out voltage threshold is detected.
Loss of Battery
In case of loss of battery (VBAT = 0 or open) the transceiver does not disturb bus communication. The maximum reverse current into the power supply system (VBAT) doesn't exceed 500 mA.
INH Pin
The transceiver is fully operational as described in the Electrical Characteristics Table over the range 6.0 V < VBAT < 18 V as measured between the GND pin and the VBAT pin. For 5.0 V < VBat < 6.0 V the bus operates in normal mode with reduced dominant output voltage and reduced receiver input voltage. High voltage wakeup is not possible (dominant output voltage is the same as in normal or high-speed mode). The transceiver operates in normal mode when 18 V > VBat > 27 V at 85C for one minute. For 0 < VBAT < 4.0 V, the bus is passive (not driven dominant) and RxD is undriven (high), regardless of the state of the TxD pin (undervoltage lockout).
The INH pin is a high-voltage highside switch used to control the ECU's regulated microcontroller power supply. After power-on, the transceiver automatically enters an intermediate standby mode, the INH output will go high (up to VBAT) turning on the external voltage regulator. The external regulator provides power to the ECU. If there is no mode change within 250 ms (typ), the transceiver re-enters the sleep mode and the INH output goes to logic 0 (floating). When the transceiver has detected a valid wake-up condition (bus HVWU traffic which exceeds the wake-up filter time delay) the INH output will become high (up to VBAT) again and the same procedure starts as described after power-on. In case of a mode change into any active mode, the sleep timer is stopped and INH stays high (up to VBAT). If the transceiver enters the sleep mode, INH goes to logic 0 (floating) after 250 ms (typ) when no wake-up signal is present
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NCV7356
Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings given in the table below are limiting values that do not lead to a
MAXIMUM RATINGS
Rating Supply Voltage, Normal Operation Short-T erm Supply Voltage, Transient Symbol VBAT VBAT.LD Condition - Load Dump; t < 500 ms Jump Start; t < 1.0 min Transient Supply Voltage Transient Supply Voltage Transient Supply Voltage CANH Voltage VBAT.TR1 VBAT.TR2 VBAT.TR3 VCANH ISO 7637/1 Pulse 1 (Note 1) ISO 7637/1 Pulses 2 (Note 1) ISO 7637/1 Pulses 3A, 3B VBAT < 27 V VBAT = 0 V Transient Bus Voltage Transient Bus Voltage Transient Bus Voltage DC Voltage on Pin LOAD DC Voltage on Pins TxD, MODE1, MODE0, RxD ESD Capability of CANH ESD Capability of Any Other Pins Maximum Latch-Up Free Current at Any Pin Maximum Power Dissipation Thermal Impedance Storage Temperature Junction Temperature Lead Temperature Soldering Reflow: (SMD styles only) VCANHTR1 VCANHTR2 VCANHTR3 VLOAD VDC VESDBUS VESD ILATCH Ptot qJA TSTG TJ Tsld At TA = 125C In Free Air - - 60 second maximum above 183C -5C/+0C allowable conditions ISO 7637/1 Pulse 1 (Note 2) ISO 7637/1 Pulses 2 (Note 2) ISO 7637/1 Pulses 3A, 3B (Note 2) Via RT > 2.0 kW - Human Body Model Eq. to Discharge 100 pF with 1.5 kW Human Body Model Eq. to Discharge 100 pF with 1.5 kW - Min -0.3 - - -50 - -200 -20 -40 -50 - -200 -40 -0.3 -4000 -2000 -500 - - -55 -40 - 40 - 100 200 40 7.0 4000 2000 500 >400 (Note 3) <70 150 150 240 peak V V V V V V V mA mW C/W C C C Max 18 40 27 - 100 200 Unit V V (peak) V V V V V
permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device.
1. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 mF blocking capacitor. 2. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF. 3. The application board shall be realized with a ground copper foil area > 150 mm2.
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ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = -40 to +125C, unless otherwise specified.)
Characteristic GENERAL Undervoltage Lock Out Supply Current, Recessive, All Active Modes Normal Mode Supply Current, Dominant High-Speed Mode Supply Current, Dominant Wake-Up Mode Supply Current, Dominant Sleep Mode Supply Current Thermal Shutdown (Note 4) Thermal Recovery (Note 4) CANH Bus Output Voltage Bus Output Voltage Low Battery Bus Output Voltage High Battery Fixed Wake-Up Output High Voltage Offset Wake-Up Output High Voltage Recessive State Output Voltage Bus Short Circuit Current Bus Leakage Current During Loss of Ground Bus Leakage Current, Bus Positive Bus Input Threshold Bus Input Threshold Low Battery Fixed Wake-Up Input High Voltage Threshold Offset Wake-Up Input High Voltage Threshold LOAD Voltage on Switched Ground Pin Voltage on Switched Ground Pin Load Resistance During Loss of Battery VLOAD VLOAD_LOB RLOAD_LOB ILOAD = 5.0 mA ILOAD = 7.0 mA, VBAT = 0 V VBAT = 0 - - RLOAD -10% - - - 0.5 1.0 RLOAD +35% V V W Voh Voh Voh VohWuFix VohWuOffset Vol -ICAN_SHORT ILKN_CAN (Note 5) ILKP_CAN Vih Vihlb VihWuFix (Note 4) VihWuOffset (Note 4) RL > 200 W, Normal, 6.0 V < VBAT < 27 V RL > 200 W, Normal, High-Speed 5.0 V < VBAT < 6.0 V RL > 75 W, High-Speed 8.0 V < VBAT < 16 V Wake-Up Mode, RL > 200 W, 11.2 V < VBAT < 27 V Wake-Up Mode, RL > 200 W, 5.5 V < VBAT < 11.2 V Recessive State or Sleep Mode, Rload = 6.5 kW VCANH = 0 V, VBAT = 27 V, TxD = 0 V Loss of Ground, VCANH = 0 V TxD High Normal, High-Speed Mode, 6.0 v VBAT v 27 V Normal, 5.0 V < VBAT < 6.0 V Sleep Mode, VBAT > 11.2 V Sleep Mode 4.4 3.4 4.2 9.9 VBAT -1.5 -0.20 50 -50 -10 2.0 1.6 6.6 VBAT -4.3 - - - - - - - - - 2.1 1.7 - - 5.1 5.1 5.1 12.5 VBAT 0.20 350 10 10 2.2 2.2 7.9 VBAT -3.25 V V V V V V mA mA mA V V V V VBATuv IBATN IBATN (Note 4) IBATN (Note 4) IBATW (Note 4) IBATS TSD TREC - VBAT = 18 V, TxD Open VBAT = 27 V, MODE0 = MODE1 = H, TxD = L, Rload = 200 W VBAT = 16 V, MODE0 = H, MODE1 = L, TxD = L, Rload = 75 W VBAT = 27 V, MODE0 = L, MODE1 = H, TxD = L, Rload = 200 W VBAT = 18 V, TxD, RxD, MODE0, MODE1 Open - - 4.0 - - - - - 155 126 - 5.0 30 70 60 30 - - 4.8 6.0 35 75 75 60 180 150 V mA mA mA mA mA C C Symbol Condition Min Typ Max Unit
4. Thresholds not tested in production, guaranteed by design. 5. Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD.
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NCV7356
ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = -40 to +125C, unless otherwise specified.)
Characteristic TXD, MODE0, MODE1 High Level Input Voltage Low Level Input Voltage TxD Pull Up Current MODE0 and 1 Pull Down Resistor RXD Low Level Output Voltage High Level Output Leakage RxD Output Current INH High Level Output Voltage Leakage Current Voh_INH IINH_lk IINH = -180 mA MODE0 = MODE1 = L, INH = 0 V VBAT -0.8 -5.0 VBAT -0.5 - - 5.0 V mA Vol_rxd Iih_rxd Irxd IRxD = 2.0 mA VRxD = 5.0 V VRxD = 5.0 V - -10 - - - - 0.4 10 70 V mA mA Vih Vil -IIL_TXD RMODE_pd 5.0 < VBAT < 27 V 5.0 < VBAT < 27 V TxD = L, MODE0 and 1 = H 5.0 < VBAT < 27 V 2.0 - 20 20 - - - - - 0.8 50 40 V V mA kW Symbol Condition Min Typ Max Unit
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TIMING MEASUREMENT LOAD CONDITIONS
Normal and High Voltage Wake-Up Mode min load / min tau min load / max tau max load / min tau max load / max tau 3.3 kohm / 540 pF 3.3 kohm / 1.2 nF 200 ohm / 5.0 nF 200 ohm / 20 nF High-Speed Mode Additional 140 ohm tool resistance to ground in parallel Additional 120 ohm tool resistance to ground in parallel
ELECTRICAL CHARACTERISTICS (5.0 V VBAT 27 V, -40C TA 125C, unless otherwise specified.) AC CHARACTERISTICS (See Figures 2, 3, and 4)
Characteristic Transmit Delay in Normal and Wake-Up Mode, Bus Rising Edge (Note 6) Transmit Delay in Wake-Up Mode to VihWU, Bus Rising Edge (Note 7) Transmit Delay in Normal Mode, Bus Falling Edge (Note 8) Transmit Delay in Wake-Up Mode, Bus Falling Edge (Note 8) Transmit Delay in High-Speed Mode, Bus Rising Edge (Note 9) Transmit Delay in High-Speed Mode, Bus Falling Edge (Note 10) Receive Delay, All Active Modes (Note 11) Receive Delay, All Active Modes (Note 11) Input Minimum Pulse Length, All Active Modes (Note 11) Wake-Up Filter Time Delay Receive Blanking Time After TxD L-H Transition TxD Timeout Reaction Time TxD Timeout Reaction Time Delay from Normal to High-Speed and High Voltage Wake-Up Mode Delay from High-Speed and High Voltage Wake-Up to Normal Mode Delay from Normal to Standby Mode Delay from Sleep to Normal Mode Delay from Standby to Sleep Mode Symbol tTr tTWUr tTf tTWU1f tTHSr tTHSf tDR tRD tmpDR tmpRD tWUF trb ttout ttoutwu tdnhs tdhsn tdsby tdsnwu tdsleep Condition min and max loads per Page 9 min and max loads per Page 9 min and max loads per Page 9 min and max loads per Page 9 min and max loads per Page 9 min and max loads per Page 9 CANH High to Low Transition CANH Low to High Transition CANH High to Low Transition CANH Low to High Transition See Figure 3 See Figure 4 Normal and High-Speed Mode Wake-Up Mode - - VBAT = 6.0 V to 27 V VBAT = 6.0 V to 27 V VBAT = 6.0 V to 27 V Min 2.0 2.0 1.8 3.0 0.1 0.1 0.3 0.3 0.15 0.15 10 0.5 - - - - - - 100 Typ - - - - - - - - - - - - 20 30 - - - - 250 Max 6.3 18 10 13.7 1.5 3.0 1.0 1.0 1.0 1.0 70 6.0 - - 30 30 500 50 1000 Unit ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms
6. The maximum signal delay time for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at minimum network time constant. These definitions are valid in both normal and High Voltage Wake-Up (HVWU) mode. 7. The maximum signal delay time for a bus rising edge in HVWU mode is measured from Vcmos_il on the TxD input pin to the VihWuMax + Vgoff max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at minimum network time constant. 8. Maximum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum network time constant, minimum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to the VihMax + Vgoff max level on CANH. These definitions are valid in both normal and HVWU mode. 9. The signal delay time in high-speed mode for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH at maximum high-speed network time constant. 10. The signal delay time in high-speed mode for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum high-speed network time constant. 11. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising (Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising and falling edges is 50 V/ms. The low level on bus is always 0V. For normal mode and high-speed mode testing the high level on bus is 4 V. For HVWU mode testing the high level on bus is VBAT - 2 V.
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BUS LOADING REQUIREMENTS
Characteristic Number of System Nodes Network Distance Between Any Two ECU Nodes Node Series Inductor Resistance (If required) Ground Offset Voltage Ground Offset Voltage Device Capacitance (Unit Load) Network Total Capacitance Device Resistance (Unit Load) Device Resistance (Min Load) Network Total Resistance Network Time Constant (Note 12) Network Time Constant in High-Speed Mode High-Speed Mode Network Resistance to GND Symbol - Bus Length Rind Vgoff Vgofflowbat Cul Ctl Rul Rmin Rtl t t Rload Min 2 - - - - 135 396 6435 2000 200 1.0 - 75 Typ - - - 0.1 x VBAT
-
Max 32 60 6.0 1.5 0.7 300 19000 6565 - 3332 4.0 1.5 135
Unit - m W V V pF pF W W W ms ms W
150 - 6490 - - - - -
12. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum value is selected to ensure proper communication modes. Not all combinations of R and C are possible.
TIMING DIAGRAMS
VTxD 50%
t
tT
VCANH
Vihmax + Vgoffmax
1V
t
tR tD VRxD 50% tF tDR
t
Figure 2. Input/Output Timing
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TIMING DIAGRAMS
VCANH Vih + Vgoff
t
tWU tWU tWUF VRxD tWU < tWUF wake-up interrupt
t
Figure 3. Wake-Up Filter Time Delay
VTxD 50%
t
VCANH
Vih
t
VRxD 50%
t
tRB
Figure 4. Receive Blanking Time
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HVWU Mode
MODE0 low MODE1 high INH VBAT MODE0/1 => High
High-Speed Mode
MODE0 high MODE0&1 => Low MODE1 low INH VBAT VBATon
Normal Mode
MODE0 high MODE1 high INH VBAT
MODE0/1 => High (If VCC_ECU on)
VBAT standby
after 250 ms -> no mode change -> no valid wake-up MODE0/1 INH low VS RxD high/low(1) CAN float
wake-up request from Bus
Sleep Mode
MODE0/1 low
(1)
INH/CAN floating
low after HVWU, high after VBAT on & VCCECU present
Figure 5. State Diagram
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NCV7356
MRA4004T3 VBAT * VBAT_ECU
Voltage Regulator INH VBAT +5 V ECU Connector to Single Wire CAN Bus 100 pF** VBAT 1 k** 9 5 RxD CAN Controller 12 CANH 10 47 mH
2.7 kW
NCV7356
MODE0 MODE1 TxD 3 4 11 2 1, 7, 8, 14 Copper Foil Heatsink >150 mm2 LOAD 6.49 kW
47 pF**
ESD Protection - MMBZ27VCLT1
GND
*Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses) ** Components to reduce EMC.
Figure 6. Application Circuitry
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PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCV7356/D

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